Digital to analog conversion systems are widely used for the purpose of converting binary words or numbers to an analog digital signal utilized for various purposes, such as the control of the tuning of a television receiver and the like. Digital to analog conversion may be implemented in a number of ways. A common approach in the past has been to use resistors in a binary weighted fashion. Such a system requires, for an n-digit binary number, n switches, one for each bit; a weighted resistive network; a reference voltage; and a summing element that adds the currents flowing in the resistive network. Obviously, such a system is restricted to only a small number of bits in the maximum sized binary word because of the large resistor range that results for n weighted resistors. Another difficulty is in maintaining the exact resistance ratios.
A more common approach which has been utilized in the past is what is known as the "R-2R" ladder network. Here the resistors all are either R or 2R in relative value and, consequently, the entire network is easier to implement than the weighted resistor type of converter. A resistor ladder converter, however, still requires very close matching of the resistors; and when the accuracy required from the converter becomes high (n becomes large), the technique becomes difficult because of the difficulty in matching the resistors.
In addition, both of the above resistor based systems for a digital to analog converter are at a substantial disadvantage for implementation in an LSI circuit; because they require a large number of pin-outs equal in number to the maximum number, n, of binary bits or digits of the largest binary word capable of being converted by the system.
In an attempt to overcome the problems which exist in implementing resistor networks into integrated circuit form and to substantially reduce the large power consumption which necessarily is inherent with a resistive network, digital to analog converters which are digital in nature have been developed. One such approach is disclosed in the patent to Ehni, U.S. Pat. No. 3,968,440. FIGS. 13 and 15 of the Ehni patent show a digital to analog converter requiring a relatively complex memory network in order to effect the desired conversion.
Another approach which utilizes digital techniques in a digital to analog converter in the form of a combined pulse rate and pulse width modulation circuit is disclosed in the patent to Ong, U.S. Pat. No. 4,096,475. This patent is directed to a system where the digital signal to be converted is changed to a periodically occuring series of digital comparison signals used to produce a number of pulses per period which increases or decreases by the value of the digital number being converted. To accomplish this the Ong system requires counters and a number of 4-bit magnitude comparator circuits of a relatively complex nature in order to effect the desired conversion. The output of the comparator network then is passed through a low-pass filter to produce the desired analog voltage.
Other techniques have been developed employing adder circuits, shift registers, and gating networks in place of the prior resistor ladder networks to produce pulse width modulated interim outputs. These outputs then are filtered to produce the desired analog output voltages. Systems of this type known to applicant are generally complex, requiring a large number of components to produce the pulse width modulated output signals utilized as the input to a low pass filter for producing the analog output voltage. Examples are the systems shown in the patents to Kaszynski, U.S. Pat. No. 3,422,423, issued Jan. 14, 1969; Mogi et al, U.S. Pat. No. 4,058,772, issued Nov. 15, 1977; Mogi, U.S. Pat. No. 4,139,840, issued Feb. 13, 1979; Buss, U.S. Pat. No. 4,093,921, issued June 6, 1978; and Dummermuth, et al., U.S. Pat. No. 3,754,235, issued Aug. 21, 1973.
It is desirable to provide a digital to analog converter circuit which is essentially entirely digital in operation except for the output filter used to develop the analog output voltage, and which is simple to implement even for the conversion of relatively large binary numbers. Furthermore, such a circuit should be capable of implementation into LSI technology, or the like, with a minimum number of input and output pins or bonding pads required.